Frequency-agile clocking has emerged as an effective power-conservation technique in mobile devices. Ideally, the system clock that serves as a primary timing reference for functional operations is switched instantly between various frequencies, scaling power consumption according to the work at hand. In practice, latency (delay) can be incurred at each frequency transition as frequency-multiplier circuitry stabilizes the system clock at its new frequency following each frequency change.
Unfortunately, conventional phase-locked loop (PLL) multipliers require relatively long re-lock times following frequency changes and thus, despite potential broad input frequency range, incur precisely the latency penalties to be avoided in a frequency-agile system. Conversely, injection-locked oscillators exhibit fast lock times, but tend to have a narrow input frequency range and thus limited frequency agility.